A storage apparatus which provides a large data storage area by using a large number of storage media such as hard disk drives (hereinafter, HDDs) has been widely used. With the increase of the data storage area, the capacity of data of each file or the like stored therein has also been increasing, and a data transfer path used for data I/O has also been required to have a high-speed data transfer performance.
In such a storage apparatus, a storage control device controls data I/O between a host computer using the storage apparatus and each storage medium such as the HDD in the storage apparatus, i.e., controls processing for a data write request or a data read request from the host. The storage control device includes, for example, a microprocessor package (hereinafter, referred to as an “MPPK”) and a data transfer controller. The MPPK includes a plurality of microprocessors (MPs) and a shared memory which is a storage device storing programs used by the MPs. The data transfer controller includes an application specific integrated circuit (hereinafter, referred to as an “ASIC”) for controlling data transfer processing in the storage apparatus and a cache memory used as a temporary storage area for data in execution of processing for the data write request and processing for the data read request from the host computer.
The data transfer controller and the host computer are coupled with each other via a front-end interface unit (hereinafter, referred to as a “FIF” unit) which is an interface circuit between a communication network on the host computer side and an internal data transfer path on the storage apparatus side. Between the data transfer controller and the storage medium such as the HDD, there is provided a back-end interface unit (hereinafter, referred to as a “BIF” unit) which is an interface circuit between an internal data transfer path controlled by the data transfer controller and a data transfer path on the recording medium side. Specific configuration examples of the above components will be described later in an embodiment of the invention of the present application.
Instead of a conventional parallel transfer method using, for example, a PCI (Peripheral Component Interconnect) bus or the like, a serial transfer method represented by, for example, PCI Express (registered trademark, hereinafter referred to as “PCIe”) has been employed for data transfer between the data transfer controller and each of the MPPK, the FIF unit, and the BIF unit. This is because the conventional parallel transfer method can no longer meet the requirements of high-speed data transfer due to technical problems such as difficulty in controlling signal synchronization timing. The entire contents of PCI Express Base Specification Revision 2.0, which is a PCIe technical standard stipulated by PCI-SIG (registered trademark, The Peripheral Component Interconnect Special Interest Group), are incorporated herein by reference.
The BIF unit is provided with a controller such for example as a SAS controller for controlling storage media coupled using an appropriate data transfer protocol such for example as Serial Attached SCSI (SAS). The SAS controller uses back-end interface control information (hereinafter, referred to as “BIF control information”) which is control information to perform interface processing between SAS control information used for the storage medium and the data write request or the data read request controlled by the MPs. The BIF control information has conventionally been stored in a buffer memory provided in the BIF unit. This is because arranging the BIF control information used by the SAS controller within the same substrate (the same package), i.e., at a position very close to the SAS controller, is advantageous in the viewpoint of such as speeding up of data transfer processing.
However, in the case where the buffer memory is provided in the BIF unit, data temporarily stored in the cache memory is again stored temporarily in the buffer memory in the BIF unit in execution of the data read or write processing. Thus, the data read or data write processing has a problem of deteriorated data transfer efficiency. Hence, a method is devised in which the buffer memory is provided in the cache memory of the data transfer controller, and the BIF control information is stored in the buffer memory. However, from a control viewpoint, the BIF control information is preferably held as close as possible to either the BIF unit or the MP involved in data transfer processing. Thus, for making the data transfer processing efficient, it is found preferable to store the BIF control information in the shared memory in the MPPK.
In the configuration in which the BIF control information is arranged in the shared memory in the MPPK, a conceivable cause for a failure in proper execution of data transfer processing requested by the BIF unit is either a failure occurring in data transfer processing between the ASIC of the data transfer controller and the BIF unit or a failure occurring in one of the MPs which reads the BIF control information stored in the shared memory. In relation to failure detection in the data transfer processing using PCIe, Patent Literature 1, for example, describes a configuration in which when a communication failure occurs in a particular lane forming a data transfer path using PCIe, failure recovery can be achieved by using another lane.